This invention relates to a programmable logic device (PLD) in which at least some of the interconnect resources are serial.
PLDs include input/output (“I/O”) regions, areas, regions, blocks or other groupings of programmable logic, and programmable interconnect resources that can be used to interconnect areas of programmable logic with each other and with the I/O regions. By properly programming or configuring the programmable logic and the programmable interconnect resources (the I/O regions also may be programmable), a user can configure a PLD to perform a desired function.
The interconnect resources of a PLD may include global interconnect resources that carry signals to and among many different parts of the device, regional interconnect resources that carry signals within a substantial portion, but less than all, of the device, and local interconnect resources that carry signals within groupings of programmable logic. Heretofore, PLD interconnect resources typically have been parallel.
PLDs have been continually increasing in size and capability. However, as the amount of programmable logic on a PLD has increased, the amount of interconnect resources, including both signal lines and switching or routing resources to create desired signal paths, also has increased. In many current PLDs, the interconnect resources may consume as much as 40% or more of the device area.
It would be desirable to be able to reduce the area consumed by interconnect resources in a programmable logic device.